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hcpl-3020/HCPL-0302 0.4 amp output current igbt gate drive optocoupler data sheet description the hcpl-3020 and HCPL-0302 consist of a gaasp led optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate-controlled devices. the voltage and current supplied by this optocoupler makes it ideally suited for directly driv - ing small or medium power igbts. for igbts with higher ratings, the hcpl-0314/3140 (0.6 a), hcpl - 3150 (0.6 a) or hcpl-3120 (2.5 a) gate drive opto-couplers can be used. features ? 0.4 a maximum peak output current ? 0.2 a minimum peak output current ? high speed response: 0.7 s maximum propagation delay over temperature range ? ultra high cmr: minimum 10 kv/s at v cm = 1000 v ? bootstrappable supply current: maximum 3 ma ? wide operating temperature range: C40c to 100c ? wide v cc operating range: 10 v to 30 v over tempera - ture range ? available in dip 8 and so-8 packages ? safety approvals: ul approval, 3750 v rms for 1 minute ? csa approval ? iec/en/din en 60747-5-2 approval v iorm = 630 v peak (hcpl-3020), v iorm = 566 v peak (HCPL-0302) applications ? isolated igbt/power mosfet gate drive ? ac and brushless dc motor drives ? industrial inverters ? air conditioner ? washing machine ? induction heater for cooker ? switching power supplies (sps) truth table led v o off low on high note: a 0.1 uf bypass capacitor must be connected between pins v cc and v ee . caution: it is advised that normal static precautions be taken in handling and assembly of this component to pre - vent damage and /or degradation which may be induced by esd. functional diagram 1 3 shield 2 4 8 6 7 5 n/ c cathode anode n/ c v cc v o n/ c v ee
2 ordering information specify part number followed by option number (if desired). example: hcpl-3020-xxxx no option = standard dip package, 50 per tube 300 = gull wing surface mount option, 50 per tube 500 = tape and reel packaging option 060 = iec/en/din en 60747-5-2, v iorm = 630 v peak xxxe = lead free option HCPL-0302-xxxx no option = standard so-8 package, 100 per tube 500 = tape and reel packaging option 060 = iec/en/din en 60747-5-2, v iorm = 566 v peak xxxe = lead free option package outline drawings hcpl-3020 standard dip package 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 6 7 8 4 3 2 1 5 typ. option code* 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) type number dimensions in millimeters and (inches). * marking code letter for option numbers. "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005)
3 hcpl-3020 gull wing surface mount option 300 HCPL-0302 small outline so-8 package 0.635 0.25 (0.025 0.010) 12 nom. 0.20 (0.008) 0.33 (0.013) 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 1.27 (0.050) note: floating lead protusion is 0.25 mm (10 mils) max. xxx yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7. 49 (0 .2 95 ) 1. 9 (0. 075 ) 0. 64 (0 .0 25 ) land pattern recommendation note: floating lead protusion is 0.15 mm (6 mils) max.
4 solder refow temperature profle recommended solder refow temperature profle (lead free) 217 ?c ramp-down 6 ? c/sec. max. ramp-up 3 ? c/sec. max. 150 - 200 ?c 260 +0/-5 ?c t 25 ?c to peak 60 to 150 sec. 20-40 sec. time within 5 ?c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time (seconds) temperature (?c ) notes: the time from 25 ?c to peak temperature = 8 minutes max. t smax = 200 ?c, t smin = 150 ?c 0 time (seconds) temperature (?c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160?c 140?c 150?c peak temp. 245?c peak temp. 240?c peak temp. 230?c soldering time 200?c preheating time 150?c, 90 + 30 sec. 2.5?c 0.5?c/sec. 3?c + 1?c/C0.5?c tight typical loose room temperature preheating rate 3?c + 1?c/C0.5?c/sec. reflow heating rate 2.5?c 0.5?c/sec. note: use of non-chlorine-activated fuxes is highly recommended note: use of non-chlorine-activated fuxes is highly recommended
5 iec/en/din en 60747-5-2 insulation characteristics (hcpl-3020 and HCPL-0302 option 060) description symbol hcpl-3020 HCPL-0302 unit installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i C iv i C iv for rated mains voltage 300 v rms i C iii i C iii for rated mains voltage 600 v rms i C ii climatic classifcation 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 630 566 v peak input to output test voltage, method b [1] v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1181 1050 v peak input to output test voltage, method a [1] v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 945 840 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 4000 v peak safety-limiting values C maximum values allowed in the event of a failure. case temperature t s 175 150 c input current [2] i s, input 230 150 ma output power [2] p s, output 600 600 mw insulation resistance at t s , v io = 500 v r s >10 9 >10 9 ? 1. refer to the optocoupler section of the isolation and control compo - nents designers catalog, under product safety regulations section, (iec/en/din en 60747-5-2), for a detailed description of method a and method b partial discharge test profles. 2. refer to the following fgure for dependence of p s and i s on ambient temperature. regulatory information the HCPL-0302/3020 has been approved by the following organizations: iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01. (option 060 only) ul approval under ul 1577, component recognition pro - gram up to v iso = 3750 v rms . file e55361. csa approval under csa component acceptance notice #5, file ca 88324. output power C p s , input current C i s 0 0 t s C case temperature C c 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma)
6 absolute maximum ratings parameter symbol min. max. units note storage temperature t s C55 125 c operating temperature t a C40 100 c average input current i f(avg) 20 ma 1 peak transient input current (<1 s pulse width, 300 pps) i f(tran) 1.0 a reverse input voltage v r 5 v high peak output current i oh(peak) 0.4 a 2 low peak output current i ol(peak) 0.4 a 2 supply voltage v cc C v ee C0.5 35 v output voltage v o(peak) C0.5 v cc v output power dissipation p o 250 mw 3 input power dissipation p i 45 mw 4 lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see package outline drawings section recommended operating conditions parameter symbol min. max. units note power supply v cc - v ee 10 30 v input current (on) i f(on) 7 12 ma input voltage (off) v f(off) C3.0 0.8 v operating temperature t a C40 100 c i nsulation and safety related specifcations parameter symbol hcpl-3020 HCPL-0302 units conditions minimum external air gap l(101) 7.1 4.9 mm measured from input terminals to output (clearance) terminals, shortest distance through air. minimum external tracking l(102) 7.4 4.8 mm measured from input terminals to output (creepage) terminals, shortest distance path along body . minimum internal plastic gap 0.08 0.08 mm through insulation distance conductor to (internal clearance) conductor, usually the straight line distance thickness between the emitter and det ector. tracking resistance cti >175 >175 v din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1)
7 switching specifcations (ac) over recommended operating conditions unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high t plh 0.1 0.2 0.7 s r g =75?, c g = 1.5 nf, 8, 9 14 output level f = 10 khz, duty cycle = 50%, 10, 11 i f = 7 ma, v cc = 30 v 12, 15 propagation delay time to low t phl 0.1 0.2 0.7 s output level propagation delay diference pdd C0.5 0.5 s 10 between any two parts or channels rise time t r 50 ns fall time t f 50 ns output high level common mode |cm h | 10 kv/s t a = 25c, v cm = 1000 v 16 11 transient immunity output low level common mode |cm l | 10 kv/s 16 12 transient immunity electrical specifcations (dc) over recommended operating conditions unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note high level output current i oh 0.15 a v o = v cc C 4 5 0.2 0.3 a v o = v cc C 10 2 2 low level output current i ol 0.15 a v o = v ee + 2.5 5 0.2 0.3 a v o = v ee + 10 4 2 high level output voltage v oh v cc C 4 v cc C 1.8 v i o = C100 ma 1 6, 7 low level output voltage v ol 0.4 1 v i o = 100 ma 3 high level supply current i cch 0.7 3 ma i o = 0 ma 5, 6 14 low level supply current i ccl 1.2 3 ma i o = 0 ma threshold input current low to high i flh 6 ma i o = 0 ma, 7, 13 v o > 5 v threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.2 1.5 1.8 v i f = 10 ma 14 temperature coefcient of input dv f /dt a C1.6 mv/c forward voltage input reverse breakdown voltage bv r 5 v i r = 10 a input capacitance c in 60 pf f = 1 mhz, v f = 0 v
8 package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary v iso 3750 v rms t a = 25c, rh < 50% 8, 9 withstand voltage input-output resistance r i-o 10 12 ? v i-o = 500 v 9 input-output capacitance c i-o 0.6 pf freq = 1 mhz notes: 1. derate linearly above 70c free air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.2 a. see application section for additional details on limiting i ol peak. 3. derate linearly above 85c, free air temperature at the rate of 4.0 mw/c. 4. input power dissipation does not require derating. 5. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage >4500 v rms for 1 second (leakage detec - tion current limit i i-o < 5 a). this test is performed before 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-2 insulation characteristics table, if applicable. 9. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. pdd is the diference between t phl and t plh between any two parts or channels under the same test conditions. 11. common mode transient immunity in the high state is the maximum tolerable |dv cm /dt| of the common mode pulse v cm to assure that the output will remain in the high state (i.e. v o > 6.0 v). 12. common mode transient immunity in a low state is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e. v o < 1.0 v). 13. this load condition approximates the gate load of a 1200 v/20 a igbt. 14. the power supply current increases when operating frequency and c g of the driven igbt increases. figure 1. v oh vs. temperature. figure 2. v oh vs. i oh . figure 3. v ol vs. temperature. (v oh -v cc ) C high output voltage drop C v -50 -2.5 t a C temperature C c 125 -25 0 0 2 5 7 5 100 50 -2.0 -1.5 -1.0 -0.5 0 i oh C output high current C a 0 0. 2 0 .4 -4 -3 -1 (v oh -v cc ) C output high voltage drop C v -2 v ol C output low voltage C v -5 0 0.39 t a C temperature C c 125 -2 5 0.44 0 2 5 7 5 100 50 0.40 0.41 0.42 0.43
9 figure 4. v ol vs. i ol . figure 5. i cc vs. temperature. figure 6. i cc vs. v cc . figure 7. i flh vs. temperature. figure 8. propagation delay vs. v cc . figure 9. propagation delay vs. i f . figure 10. propagation delay vs. tempera - figure 11. propagation delay vs. r g . figure 12. propagation delay vs. c g. v ol C output low voltage drop C v 0 0 i ol C output low current C a 0. 4 5 0. 2 1 4 0. 1 0 .3 3 2 i cc C supply current C ma -5 0 0 t a C temperature C c 125 -2 5 1. 4 0 2 5 7 5 100 50 0. 4 0. 6 0. 8 1. 2 0. 2 1. 0 i cc l i cc h i cc C supply current C ma 10 0 v cc C supply voltage C v 30 15 1. 2 20 25 0. 4 0. 8 0. 2 0. 6 1. 0 i cc l i cc h i flh C low to high current threshold C ma -5 0 1. 5 t a C temperature C c 125 -2 5 3. 5 0 2 5 7 5 100 50 2. 0 2. 5 3. 0 t p C propagation delay C ns 10 0 v cc C supply voltage C v 30 400 15 25 20 100 200 300 t plh t phl t p C propagation delay C ns 6 0 i f C forward led current C ma 18 400 9 1 5 12 100 200 300 -5 0 0 t a C temperature C c 125 -2 5 500 0 2 5 7 5 100 50 100 200 300 400 t p C propagation delay C ns t plh t phl t p C propagation delay C ns 0 200 rg C series load resistance C ? 200 400 50 150 100 250 300 350 t plh t phl t p C propagation delay C ns 0 0 cg C load capacitance C nf 100 400 20 80 60 100 200 300 t plh t phl 40
10 figure 13. transfer characteristics. figure 14. input current vs. forward voltage. figure 15. propagation delay test circuits and waveforms. figure 16. cmr test circuits and waveforms. 0.1 f v cc = 15 to 30 v 75 ? 1 3 i f = 7 to 16 ma v o + ? + ? 2 4 8 6 7 5 10 khz 50% duty cycle 500 ? 1.5 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 f v cc = 30 v 1 3 i f v o + ? + ? 2 4 8 6 7 5 a + ? b v cm = 1000 v 5 v v cm ? t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh ? t v cm v t = i f C forward current C ma 1.2 0 v f C forward voltage C v 1.8 25 1.4 1.6 5 10 15 20 v o C output voltage C v 0 -5 i f C forward led current C ma 6 25 15 1 35 2 3 4 5 5 0 10 20 30
11 applications information eliminating negative igbt gate drive to keep the igbt frmly of, the hcpl-3020 and hcpl- 0302 have a very low maximum v ol specifcation of 1.0 v. minimizing r g and the lead inductance from the hcpl-3020 or HCPL-0302 to the igbt gate and emitter (possibly by mounting the hcpl-3020 or HCPL-0302 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 17. care should be taken with such a pc board design to avoid routing the igbt collector or emit - ter traces close to the hcpl-3020 or HCPL-0302 input as this can result in unwanted coupling of transient signals into the input of hcpl-3020 or HCPL-0302 and degrade performance. (if the igbt drain must be routed near the hcpl-3020 or HCPL-0302 input, then the led should be reverse biased when in the of state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl-3020 or HCPL-0302. figure 17. recommended led drive and application circuit for hcpl-3020 and HCPL-0302. + hvdc 3-phase ac - hvdc 0.1 f v cc = 15 v 1 3 + ? 2 4 8 6 7 5 hcpl-3020/0302 rg q1 q2 270 ? +5 v control input 74xxx open collector
12 selecting the gate resistor (r g ) for hcpl-3020 step 1: calculate r g minimum from the i ol peak specifcation. the igbt and r g in figure 17 can be analyzed as a simple rc circuit with a voltage supplied by the hcpl-3020. r g v cc C v ol i olpeak = 24 - 1 0.4 = 57.5 ? the v ol value of 1 v in the previous equation is the v ol at the peak current of 0.4 a. (see figure 4). step 2: check the hcpl-3020 power dissipation and increase r g if necessary. the hcpl-3020 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o(switching) = i cc ? v cc + e sw (r g ;q g ) ? f = (i ccbias + k icc ? q g ? f ) ? v cc + e sw (r g ;q g ) ? f where k icc ? q g ? f is the increase in i cc due to switching and k icc is a constant of 0.001 ma/(nc*khz). for the circuit in figure 17 with i f (worst case) = 10 ma, r g = 57.5 ?, max duty cycle = 80%, q g = 100 nc, f = 20 khz and t amax = 85c: p e = 10 ma ? 1.8 v ? 0.8 = 14 mw p o = [3 ma + (0.001 ma/nc ? khz) ? 20 khz ? 100 nc] ? 24 v + 0.3 m j ? 20 khz = 126 mw < 250 mw (p o(max) ) @ 85c the value of 3 ma for i cc in the previous equation is the max. i cc over entire operating temperature range. since p o for this case is less than p o(max) , r g = 57.5 ? is alright for the power dissipation. figure 18. energy dissipated in the hcpl-3020 and HCPL-0302 and for each igbt switching cycle. esw C energy per switching cycle C j 0 0 rg C gate resistance C ? 100 1. 5 20 4. 0 40 1. 0 60 80 3. 5 qg = 50 nc qg = 100 nc qg = 200 nc qg = 400 nc 3. 0 2. 0 0. 5 2. 5
13 led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocou - pler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 19. the hcpl-3020 and HCPL-0302 improve cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the ca - pacitive coupling between the led and optocoupler pins 5-8 as shown in figure 20. this capacitive coupling causes figure 19. optocoupler input to output capacitance model for unshielded optocouplers. figure 20. optocoupler input to output capacitance model for shielded optocouplers. figure 21. equivalent circuit for fgure 15 during common mode transient. figure 22. not recommended open collector drive circuit. figure 23. recommended led drive circuit for ultra-high cmr ipm dead time and propagation delay specifcations. 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during Cdv cm /dt . +5 v + C v cc = 18 v ? ? ? ? ? ? 0. 1 f + C C 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode tran - sients. for example, the recommended application circuit (figure 17), can achieve 10 kv/s cmr while minimizing component complexity. techniques to keep the led in the proper state are dis - cussed in the next two sections.
14 dead time and propagation delay specifcations the hcpl-3020 and HCPL-0302 include a propagation delay diference (pdd) specifcation intended to help designers minimize dead time in their power inverter designs. dead time is the time high and low side power transistors are of. any overlap in ql and q2 conduction will result in large currents fowing through the power devices from the high voltage to the low-voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led1) so that under worst-case conditions, transistor q1 has just turned of when transistor q2 turns on, as shown in figure 24. the amount of delay necessary to achieve this condition is equal to the maximum value of the propa - gation delay diference specifcation, pdd max, which is specifed to be 500 ns over the operating temperature range of C40 to 100c. delaying the led signal by the maximum propagation delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propag a tion delay diference specifcation as shown in figure 25. the maximum dead time for the hcpl-3020 and HCPL-0302 is 1 ms (= 0.5 s C (C0.5 s)) over the operating temperature range of C40c to 100c. cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 7 ma provides adequate margin over the maximum i flh of 6 ma to achieve 10 kv/s cmr. cmr with the led of (cmr l ) a high cmr led drive circuit must keep the led of (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 21, the current fow - ing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) the led will remain of and no common mode failure will occur. the open collector drive circuit, shown in figure 22, cannot keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr 1 performance. the alternative drive circuit, which likes the recommended application circuit (figure 17), does achieve ultra high cmr performance by shunting the led in the of state. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
15 figure 24. minimum led skew for zero dead time. figure 25. waveforms for dead time. t phl max t plh mi n pdd* max = (t phl - t plh ) max = t phl max - t plh mi n *pdd = propagation delay difference note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t plh mi n maximum dead time (due to optocoupler) = (t phl max - t phl mi n ) + (t plh max - t plh mi n ) = (t phl max - t plh mi n ) C (t phl min - t plh max ) = pdd* max C pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl mi n t phl max t plh max pdd* max (t phl- t plh ) max for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, pte. in the united states and other countries. data subject to change. copyright ? 2006 avago technologies pte. all rights reserved. obsoletes 5989-2947en av01-0367en - august 2, 2006

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